Research Catalog

Layout design and verification

Title
  1. Layout design and verification / edited by T. Ohtsuki.
Published by
  1. Amsterdam ; New York : North-Holland ; New York, N.Y., U.S.A. : Sole distributors for the U.S.A. and Canada, Elsevier Science Pub. Co., 1986.

Items in the library and off-site

Filter by

Displaying 1 item

StatusFormatAccessCall numberItem location
Status
Request for on-site useRequest scan
How do I pick up this item and when will it be ready?
FormatTextAccessUse in libraryCall numberTK7874 .L318 1986Item locationOff-site

Details

Additional authors
  1. Ohtsuki, T. (Tatsuo), 1940-
Description
  1. ix, 356 pages : illustrations; 25 cm.
Series statement
  1. Advances in CAD for VLSI ; v. 4
Uniform title
  1. Advances in CAD for VLSI ; v. 4.
Subject
  1. Integrated circuits > Very large scale integration > Design and construction
  2. Integrated circuits > Verification
  3. Integrated circuit layout
  4. Entwurf
  5. Layout Mikroelektronik
  6. VLSI
  7. Circuits intégrés à très grande échelle
  8. Entwurf
  9. Layout (Mikroelektronik)
  10. VLSI
Owning institution
  1. Princeton University Library
Bibliography (note)
  1. Includes bibliographies and indexes.